Display Port to LVDS変換ブリッジ： PTN3460BS , Display Port to LVDS Bridge IC 56-Pin HVQFN EP （NXP）

製品名
Display Port to LVDS変換ブリッジ： PTN3460BS
　
特徴　

　デバイス
　　・EDID ROM エミュレーションにより、EDID ROMなしパネルに対応。
　　・ EDID structure v1.3

　DisplayPort
　・Compliant to DP v1.2a and v1.1a
　・Compliant to eDP v1.2 and v1.1
　・Supports Main Link 2レーン
　　・ Reduced Bit Rate (1.62 Gbit/s) 、High Bit Rate (2.7 Gbit/s)
　・Supports 1 Mbit/s AUX channel

LVDS transmitter features
・Compatible with ANSI/TIA/EIA-644-A-2001 standard
・RGB data packing as per JEIDA and VESA data formats
・ pixel clock frequency from 6 MHz to 112 MHz
・single LVDS bus operation up to 112 mega pixels per second
・ dual LVDS bus operation up to 224 mega pixels per second
・ color depth options: 18 bpp, 24 bpp
・ 1920 x 1200 at 60 Hz resolution in dual LVDS bus mode



In English－－－－－－－－－－－－－－－－－－－－

Product
　PTN3460BS , Display Port to LVDS Bridge IC 56-Pin HVQFN EP （NXP）

Features

　Device features

・Embedded microcontroller and on-chip Non-Volatile Memory (NVM)
　allow for flexibility in firmware updates
・LVDS panel power-up (/down) sequencing control
・Firmware controlled panel power-up (/down) sequence timing parameters
・No external timing reference needed
・EDID ROM emulation to support panels with no EDID ROM. Emulation 　　
　　ON/OFF is set via configuration pin CFG4
ー Supports EDID structure v1.3
ーOn-chip EDID emulation up to seven different EDID data structures
ーeDP complying PWM signal generation or
　　　 PWM signal pass through from eDP source

　DisplayPort receiver features

・Compliant to DP v1.2a and v1.1a
・Compliant to eDP v1.2 and v1.1
・Supports Main Link operation with one or two lanes
　・(select through configuration pin CFG3)
・ Supports Main Link rate: Reduced Bit Rate (1.62 Gbit/s)
　　and High Bit Rate (2.7 Gbit/s)
・Supports 1 Mbit/s AUX channel
・Supports Native AUX and I2C-over-AUX transactions
・Supports down spreading to minimize EMI
Integrated 50 Ω termination resistors provide impedance matching on both Main Link lanes and AUX channel
High performance Auto Receive Equalization enabling optimal channel compensation, device placement flexibility and power saving at CPU/GPU
Supports eDP authentication options: Alternate Scrambler Seed Reset (ASSR) and Alternate Framing
Supports Full Link training
Supports DisplayPort symbol error rate measurements
Supports PCB routing flexibility by programming for:
AUX P/N swapping
DP Main Link P/N swapping

LVDS transmitter features

Compatible with ANSI/TIA/EIA-644-A-2001 standard
Supports RGB data packing as per JEIDA and VESA data formats
Supports pixel clock frequency from 6 MHz to 112 MHz
Supports single LVDS bus operation up to 112 mega pixels per second
Supports dual LVDS bus operation up to 224 mega pixels per second
Supports color depth options: 18 bpp, 24 bpp
Programmable center spreading of pixel clock frequency to minimize EMI
Supports 1920 x 1200 at 60 Hz resolution in dual LVDS bus mode
Programmable LVDS signal swing to pre-compensate for channel attenuation or allow for power saving
Supports PCB routing flexibility by programming for:
LVDS bus swapping
Channel swapping
Differential signal pair swapping
Supports Data Enable polarity programming
DDC control for EDID ROM access; I2C-bus interface up to 400 kbit/s